Reliable Silicon Systems Lab

Publications

Selected Recent Publications

A. Orzechowski, L. Lugosch, H. Shu, R. Yang, W. Li, and B. H. Meyer,
“A data-driven framework for medium-term electric vehicle charging demand forecasting,” Energy and AI, vol. 14, pp. 1–11, 2023.
O. Therrien, M. Amein, Z. Xiong, W. J. Gross, and B. H. Meyer,
“SSS3D: Fast neural architecture search for efficient three-dimensional semantic segmentation,” in 2023 tinyML research symposium, 2023, pp. 1–6.
J. Mehta, G. Richard, L. Lugosch, D. Yu, and B. H. Meyer,
“DT-DS: CAN intrusion detection with decision tree ensembles,” ACM Trans. Cyber-Phys. Syst., vol. 7, no. 1, pp. 1–27, Mar. 2023.
H.-Y. Chang, S. H. Mozafari, C. Chen, J. J. Clark, B. H. Meyer, and W. J. Gross,
“PipeBERT: High-throughput BERT inference for ARM Big.LITTLE multi-core processors,” Journal of Signal Processing Systems, Oct. 2022.
M. Búr, K. Marussy, B. H. Meyer, and D. Varró,
“Worst-case execution time calculation for query-based monitors by witness generation,” ACM Trans. Embed. Comput. Syst., vol. 20, no. 6, Oct. 2021.
W. J. Gross, B. H. Meyer, and A. Ardakani,
“Hardware-aware design for edge intelligence,” IEEE Open Journal of Circuits and Systems, pp. 1–14, 2020.

Full Bibliography

Journals
Conferences
Posters and Symposia
Book Chapters

Journal Articles

A. Orzechowski, L. Lugosch, H. Shu, R. Yang, W. Li, and B. H. Meyer,
“A data-driven framework for medium-term electric vehicle charging demand forecasting,” Energy and AI, vol. 14, pp. 1–11, 2023.
J. Mehta, G. Richard, L. Lugosch, D. Yu, and B. H. Meyer,
“DT-DS: CAN intrusion detection with decision tree ensembles,” ACM Trans. Cyber-Phys. Syst., vol. 7, no. 1, pp. 1–27, Mar. 2023.
H.-Y. Chang, S. H. Mozafari, C. Chen, J. J. Clark, B. H. Meyer, and W. J. Gross,
“PipeBERT: High-throughput BERT inference for ARM Big.LITTLE multi-core processors,” Journal of Signal Processing Systems, Oct. 2022.
S. H. Mozafari, J. J. Clark, W. J. Gross, and B. H. Meyer,
“Implementing convolutional neural networks using hartley stochastic computing with adaptive rate feature map compression,” IEEE Open Journal of Circuits and Systems, vol. 2, pp. 805–819, 2021.
M. Búr, K. Marussy, B. H. Meyer, and D. Varró,
“Worst-case execution time calculation for query-based monitors by witness generation,” ACM Trans. Embed. Comput. Syst., vol. 20, no. 6, Oct. 2021.
W. J. Gross, B. H. Meyer, and A. Ardakani,
“Hardware-aware design for edge intelligence,” IEEE Open Journal of Circuits and Systems, pp. 1–14, 2020.
N. Onizawa, S. C. Smithson, B. H. Meyer, W. J. Gross, and T. Hanyu,
“In-hardware training chip based on CMOS invertible logic for machine learning,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 67, no. 1, pp. 1–10, 2020.
Z. Al-bayati, Y. Sun, H. Zeng, M. D. Natale, Q. Zhu, and B. H. Meyer,
“Partitioning and selection of data consistency mechanisms for multicore real-time systems,” ACM Trans. Embed. Comput. Syst., vol. 18, no. 4, pp. 35:1–35:28, Jun. 2019.
S. H. Mozafari and B. H. Meyer,
“Characterizing the effectiveness of hot sparing on cost and performance-per-watt in application specific SIMT,” Integration, the VLSI Journal, vol. 69, pp. 198–209, 2019.
S. C. Smithson, N. Onizawa, B. H. Meyer, W. J. Gross, and T. Hanyu,
“Efficient CMOS invertible logic using stochastic computing,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 66, no. 6, pp. 2263–2274, 2019.
J. Caplan, Z. Al-bayati, H. Zeng, and B. H. Meyer,
“Mapping and scheduling mixed-criticality systems with on-demand redundancy,” IEEE Transactions on Computers, vol. 64, no. 7, pp. 582–588, Apr. 2018.
S. H. Mozafari and B. H. Meyer,
“Efficient performance evaluation of multi-core SIMT processors with hot redundancy,” IEEE Transactions on Emerging Topics in Computing (TETC), vol. 6, no. 4, pp. 498–510, 2018.
M. I. Mera, J. Caplan, S. H. Mozafari, B. H. Meyer, and P. Milder,
“Area, throughput, and power trade-offs for FPGA- and ASIC-based execution stream compression,” ACM Trans. Embed. Comput. Syst., vol. 16, no. 4, pp. 96:1–96:20, May 2017.
R. Zhang, B. H. Meyer, K. Wang, M. R. Stan, and K. Skadron,
“Tolerating the consequences of multiple EM-induced C4 bump failures,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 24, no. 6, pp. 2335–2344, 2016.
D. Stamoulis, K. Tsoumanis, D. Rodopoulos, B. H. Meyer, K. Pekmestzi, D. Soudris, and Z. Zilic,
“Efficient variability analysis of arithmetic units using linear regression techniques,” Analog Integrated Circuits and Signal Processing, vol. 87, no. 2, pp. 249–261, 2016.
V. Lari, J. Teich, A. Tanase, M. Witterauf, F. Khosravi, and B. H. Meyer,
“Techniques for on-demand structural redundancy for massively parallel processor arrays,” Journal of Systems Architecture, vol. 61, no. 10, pp. 615–627, 2015.
B. H. Meyer, A. S. Hartman, and D. E. Thomas,
“Cost-effective lifetime and yield optimization for NoC-based MPSoCs,” ACM Trans. Des. Autom. Electron. Syst., vol. 19, no. 2, pp. 12:1–12:33, Mar. 2014.
L. G. Szafaryn, B. H. Meyer, and K. Skadron,
“Evaluating overheads of multibit soft-error protection in the processor core,” IEEE Micro, vol. 33, no. 4, pp. 56–65, Jul. 2013.
K. Sankaranarayanan, B. H. Meyer, W. Huang, R. Ribando, H. Haj-Hariri, M. R. Stan, and K. Skadron,
“Architectural implications of spatial thermal filtering,” Integr. VLSI J., vol. 46, no. 1, pp. 44–56, Jan. 2013.
K. Sankaranarayanan, B. H. Meyer, M. R. Stan, and K. Skadron,
“Thermal benefit of multi-core floorplanning: A limits study,” Sustainable Computing: Informatics and Systems, vol. 1, no. 4, pp. 286–293, 2011.
B. H. Meyer and D. E. Thomas,
“Rethinking the synthesis of buses, data mapping, and memory allocation for MPSoC,” Design Automation for Embedded Systems, vol. 13, no. 1, pp. 73–88, 2009.
J. M. Paul and B. H. Meyer,
“Amdahl’s law revisited for single chip systems,” International Journal of Parallel Programming, vol. 35, no. 2, pp. 101–123, 2007.
B. H. Meyer, J. J. Pieper, J. M. Paul, J. E. Nelson, S. M. Pieper, and A. G. Rowe,
“Power-performance simulation and design strategies for single-chip heterogeneous multiprocessors,” IEEE Transactions on Computers, vol. 54, no. 6, pp. 684–697, Jun. 2005.

Conference Proceedings

S. H. Mozafari, J. J. Clark, W. J. Gross, and B. H. Meyer,
“Efficient 1D grouped convolution for PyTorch, a case study: Fast on-device fine-tuning for SqueezeBERT,” in 2023 IEEE international conference on application-specific systems, architectures, and processors (ASAP), 2023, pp. 1–8.
L. Shen, I. Amara, R. Li, B. H. Meyer, W. J. Gross, and J. J. Clark,
“Fast fine-tuning using curriculum domain adaptation,” in 20th IEEE conference on robots and vision, 2023, pp. 1–12.
H.-Y. Chang, S. H. Mozafari, J. J. Clark, B. H. Meyer, and W. J. Gross,
“High-throughput edge inference for BERT models via neural architecture search and pipeline.” pp. 1–6, 2023.
S. H. Mozafari, J. J. Clark, W. J. Gross, and B. H. Meyer,
“Training acceleration of frequency domain CNNs using activation compression,” in 2023 IEEE internaional symposium on circuit and systems (ISCAS), 2023, pp. 1–5.
Z. Xiong, M. Amein, O. Therrien, W. J. Gross, and B. H. Meyer,
“FMAS: Fast multi-objective SuperNet architecture search for semantic segmentation,” in 2023 tinyML research symposium, 2023, pp. 1–6.
O. Therrien, M. Amein, Z. Xiong, W. J. Gross, and B. H. Meyer,
“SSS3D: Fast neural architecture search for efficient three-dimensional semantic segmentation,” in 2023 tinyML research symposium, 2023, pp. 1–6.
C. Le, A. Ardakani, A. Ardakani, H. Zhang, Y. Chen, J. J. Clark, B. H. Meyer, and W. J. Gross,
“Efficient two-stage progressive quantization of BERT,” in Proceedings of the third workshop on simple and efficient natural language processing (SustaiNLP), 2022, pp. 1–9.
M. Abdelgawad, S. H. Mozafari, J. J. Clark, B. H. Meyer, and W. J. Gross,
“BERTPerf: Inference latency predictor for BERT on ARM big.LITTLE multi-core processors,” in 2022 IEEE workshop on signal processing systems (SiPS), 2022, pp. 1–6.
M. Amein, Z. Xiong, O. Therrien, B. H. Meyer, and W. J. Gross,
“Work-in-progress: SuperNAS: Fast multi-objective SuperNet architecture search for semantic segmentation,” in 2022 ACM/IEEE international conference on compilers, architecture, and synthesis for embedded systems (CASES), 2022, pp. 35–36.
N. Firouzian, S. H. Mozafari, J. J. Clark, W. J. Gross, and B. H. Meyer,
“Work-in-progress: Utilizing latency and accuracy predictors for efficient hardware-aware NAS,” in 2022 ACM/IEEE international conference on hardware/software codesign and system synthesis (CODES+ISSS), 2022, pp. 15–16.
I. Amara, M. Ziaeefard, B. H. Meyer, W. J. Gross, and and James J. Clark,
“CES-KD: Curriculum-based expert selection for guided knowledge distillation,” in 2022 IEEE international conference on pattern recognition (ICPR), 2022, pp. 1–7.
M. Kornelsen, S. H. Mozafari, J. J. Clark, B. H. Meyer, and W. J. Gross,
“Fast heterogeneous task mapping for reducing edge DNN latency,” in 2022 IEEE international conference on application-specific systems, architectures, and processors (ASAP), 2022, pp. 1–8.
L. Shen, M. Ziaeefard, B. H. Meyer, W. J. Gross, and J. J. Clark,
“Conjugate adder net (CAddNet) - a space-efficient approximate CNN,” in 2022 IEEE/CVF conference on computer vision and pattern recognition workshops (CVPRW), 2022, pp. 2792–2796.
D. Vucetic, M. Tayaranian, M. Ziaeefard, J. J. Clark, B. H. Meyer, and W. J. Gross,
“Efficient fine-tuning of BERT models on the edge,” in 2022 IEEE international symposium on circuit and systems (ISCAS), 2022, pp. 1838–1842.
S. H. Mozafari, J. J. Clark, W. J. Gross, and B. H. Meyer,
“Hartley stochastic computing for convolutional neural networks,” in 2021 IEEE workshop on signal processing systems (SiPS), 2021, pp. 1–6.
L. Lugosch, B. H. Meyer, D. Nowrouzezahrai, and M. Ravanelli,
“Using speech synthesis to train end-to-end spoken language understanding models,” in 45th international conference on acoustics, speech, and signal processing (ICASSP), 2020, pp. 1–5.
Z. Yin, W. J. Gross, and B. H. Meyer,
“Probabilistic sequential multi-objective optimization of convolutional neural networks,” in 2020 design, automation test in europe conference exhibition (DATE), 2020, pp. 1–6.
D. Yu, M. Vaquier, E. Laflamme, G. Doucette-Poirier, J. Tremblay, and B. H. Meyer,
“ARINC-825TBv2: A hardware-in-the-loop simulation platform for aerospace security research,” in Proceedings of the 30th international workshop on rapid system prototyping, RSP 2019, 2019, pp. 29–35.
N. Onizawa, K. Nishino, S. C. Smithson, B. H. Meyer, W. Gross, H. Yamagata, H. Fujita, and T. Hanyu,
“A design framework for invertible logic,” in 2019 conference record of the fifty third asilomar conference on signals, systems and computers, 2019, pp. 1–5.
A. Ardakani, Z. Ji, S. C. Smithson, B. H. Meyer, and W. J. Gross,
“Learning recurrent binary/ternary weights,” in 2019 seventh international conference on learning representations (ICLR), 2019, pp. 1–14.
K. Nishino, S. C. Smithson, N. Onizawa, B. H. Meyer, W. J. Gross, H. Yamagata, H. Fujita, and T. Hanyu,
“Study of stochastic invertible multiplier designs,” in 2018 25th IEEE international conference on electronics, circuits and systems (ICECS), 2018, pp. 649–650.
C. Ma, A. Mahajan, and B. H. Meyer,
“Multi-armed bandits for efficient lifetime estimation in MPSoC design,” in 2017 design, automation test in europe conference exhibition (DATE), 2017, pp. 1–6.
S. C. Smithson, G. Yang, W. J. Gross, and B. H. Meyer,
“Neural networks designing neural networks: Multi-objective hyper-parameter optimization,” in Computer-aided design (ICCAD), 2016 IEEE/ACM international conference on, 2016, pp. 1–8.
S. D. Dagondon, W. J. Gross, and B. H. Meyer,
“Sparse-clustered network with selective decoding for internet traffic classification,” in Signal processing systems (SiPS), 2016 IEEE workshop on, 2016, pp. 1–6.
S. C. Smithson, K. Boga, A. Ardakani, B. H. Meyer, and W. J. Gross,
“SS-stochastic: Stochastic computing can improve upon digital spiking neural networks,” in Signal processing systems (SiPS), 2015 IEEE workshop on, 2016, pp. 1–6.
M. T. Kassis, Y. R. Akaveeti, B. H. Meyer, and R. Khazaka,
“Parallel transient simulation of power delivery networks using model order reduction,” in Electrical performance of electronic packaging and systems (EPEPS), 2015 IEEE 25th conference on, 2016, pp. 1–3.
Z. Al-bayati, B. H. Meyer, and H. Zeng,
“Fault-tolerant scheduling of multicore mixed-criticality systems under permanent failures,” in 2016 IEEE international symposium on defect and fault tolerance in VLSI and nanotechnology systems (DFTS), 2016, pp. 1–6.
M. Liu and B. H. Meyer,
“Bounding error detection latency in safety critical systems with enhanced execution fingerprinting,” in 2016 IEEE international symposium on defect and fault tolerance in VLSI and nanotechnology systems (DFTS), 2016, pp. 1–6.
Z. Al-bayati, J. Caplan, B. H. Meyer, and H. Zeng,
“A four-mode model for efficient fault-tolerant mixed-criticality systems,” in 2016 design, automation test in europe conference exhibition (DATE), 2016, pp. 97–102.
D. Stamoulis, S. Corbetta, D. Rodopoulos, P. Weckx, P. Debacker, B. H. Meyer, B. Kaczer, P. Raghavan, D. Soudris, F. Catthoor, and Z. Zilic,
“Capturing true workload dependency of BTI-induced degradation in CPU components,” in Proceedings of the 26th edition of the great lakes symposium on VLSI, 2016, pp. 373–376.
S. H. Mozafari and B. H. Meyer,
“Hot spare components for performance-cost improvement in multi-core SIMT,” in 2015 IEEE international symposium on defect and fault tolerance in VLSI and nanotechnology systems (DFTS), 2015, pp. 53–59.
B. Nahar and B. H. Meyer,
“RotR: Rotational redundant task mapping for fail-operational MPSoCs,” in 2015 IEEE international symposium on defect and fault tolerance in VLSI and nanotechnology systems (DFTS), 2015, pp. 21–28.
R. Zhang, K. Mazumdar, B. H. Meyer, K. Wang, K. Skadron, and M. R. Stan,
“Transient voltage noise in charge-recycled power delivery networks for many-layer 3D-IC,” in Low power electronics and design (ISLPED), 2015 IEEE/ACM international symposium on, 2015, pp. 152–158.
V. Lari, A. Tanase, J. Teich, M. Witterauf, F. Khosravi, F. Hannig, and B. H. Meyer,
“A co-design approach for fault-tolerant loop execution on coarse-grained reconfigurable arrays,” in Adaptive hardware and systems (AHS), 2015 NASA/ESA conference on, 2015, pp. 1–8.
R. Zhang, K. Mazumdar, B. H. Meyer, K. Wang, K. Skadron, and M. Stan,
“A cross-layer design exploration of charge-recycled power-delivery in many-layer 3D-IC,” in 2015 52nd ACM/EDAC/IEEE design automation conference (DAC), 2015, pp. 1–6.
S. H. Mozafari, B. H. Meyer, and K. Skadron,
“Yield-aware performance-cost characterization for multi-core SIMT,” in Proceedings of the 25th edition of the great lakes symposium on VLSI, 2015, pp. 237–240.
D. Stamoulis, D. Rodopoulos, B. H. Meyer, D. Soudris, F. Catthoor, and Z. Zilic,
“Efficient reliability analysis of processor datapath using atomistic BTI variability models,” in Proceedings of the 25th edition of the great lakes symposium on VLSI, 2015, pp. 57–62.
Z. Al-bayati, Y. Sun, H. Zeng, M. D. Natale, Q. Zhu, and B. H. Meyer,
“Task placement and selection of data consistency mechanisms for real-time multicore applications,” in 21st IEEE real-time and embedded technology and applications symposium, 2015, pp. 172–181.
D. Stamoulis, D. Rodopoulos, B. H. Meyer, D. Soudris, and Z. Zilic,
“Linear regression techniques for efficient analysis of transistor variability,” in Electronics, circuits and systems (ICECS), 2014 21st IEEE international conference on, 2014, pp. 267–270.
R. Zhang, K. Wang, B. H. Meyer, M. R. Stan, and K. Skadron,
“Architecture implications of pads as a scarce resource,” in 2014 ACM/IEEE 41st international symposium on computer architecture (ISCA), 2014, pp. 373–384.
K. Wang, B. H. Meyer, R. Zhang, M. Stan, and K. Skadron,
“Walking pads: Managing C4 placement for transient voltage noise minimization,” in 2014 51st ACM/EDAC/IEEE design automation conference (DAC), 2014, pp. 1–6.
C. Jiang, M. Liu, and B. H. Meyer,
“MB-FICA: Multi-bit fault injection and coverage analysis,” in Proceedings of the 24th edition of the great lakes symposium on VLSI, 2014, pp. 205–210.
J. Caplan, M. I. Mera, P. Milder, and B. H. Meyer,
“Trade-offs in execution signature compression for reliable processor systems,” in 2014 design, automation test in europe conference exhibition (DATE), 2014, pp. 1–6.
K. Wang, B. H. Meyer, R. Zhang, K. Skadron, and M. Stan,
“Walking pads: Fast power-supply pad-placement optimization,” in 2014 19th asia and south pacific design automation conference (ASP-DAC), 2014, pp. 537–543.
B. H. Meyer, M. Liu, J. Caplan, and G. Z. Kostadinov,
“Rapid, tunable error detection with execution fingerprinting,” in SAE 2013 AeroTech congress and exhibition, 2013, pp. 1–13.
G. G. Faust, R. Zhang, K. Skadron, M. R. Stan, and B. H. Meyer,
“ArchFP: Rapid prototyping of pre-RTL floorplans,” in VLSI and system-on-chip, 2012 (VLSI-SoC), IEEE/IFIP 20th international conference on, 2012, pp. 183–188.
B. H. Meyer, B. H. Calhoun, J. Lach, and K. Skadron,
“Cost-effective safety and fault localization using distributed temporal redundancy,” in Compilers, architectures and synthesis for embedded systems (CASES), 2011 proceedings of the 14th international conference on, 2011, pp. 125–134.
B. H. Meyer, N. George, B. Calhoun, J. Lach, and K. Skadron,
“Reducing the cost of redundant execution in safety-critical systems using relaxed dedication,” in 2011 design, automation test in europe, 2011, pp. 1–6.
A. S. Hartman, D. E. Thomas, and B. H. Meyer,
“A case for lifetime-aware task mapping in embedded chip multiprocessors,” in Hardware/software codesign and system synthesis (CODES+ISSS), 2010 IEEE/ACM/IFIP international conference on, 2010, pp. 145–154.
Z. Qi, B. H. Meyer, W. Huang, R. J. Ribando, K. Skadron, and M. R. Stan,
“Temperature-to-power mapping,” in Computer design (ICCD), 2010 IEEE international conference on, 2010, pp. 384–389.
B. H. Meyer, A. S. Hartman, and D. E. Thomas,
“Slack allocation for yield improvement in NoC-based MPSoCs,” in Quality electronic design (ISQED), 2010 11th international symposium on, 2010, pp. 738–746.
B. H. Meyer, A. S. Hartman, and D. E. Thomas,
“Cost-effective slack allocation for lifetime improvement in NoC-based MPSoCs,” in 2010 design, automation test in europe conference exhibition (DATE 2010), 2010, pp. 1596–1601.
B. H. Meyer and D. E. Thomas,
“Simultaneous synthesis of buses, data mapping and memory allocation for MPSoC,” in Hardware/software codesign and system synthesis (CODES+ISSS), 2007 5th IEEE/ACM/IFIP international conference on, 2007, pp. 3–8.
B. H. Meyer and D. E. Thomas,
“Rethinking automated synthesis of MPSoC architectures,” in 2007 IEEE international parallel and distributed processing symposium, 2007, pp. 1–6.

Posters and Symposia

I. Amara, M. Ziaeefard, B. H. Meyer, W. J. Gross, and J. J. Clark,
“On the importance of integrating curriculum design for teacher assistant-based knowledge distillation,” in 2022 edge intelligence workshop, 2022.
A. Ardakani, A. Ardakani, B. H. Meyer, J. J. Clark, and W. J. Gross,
“Standard deviation-based quantization for deep neural networks,” in 2022 edge intelligence workshop, 2022.
H.-Y. Chang, S. H. Mozafari, J. J. Clark, W. J. Gross, and B. H. Meyer,
“NAS plus pipeline for high throughput inference BERT,” in 2022 edge intelligence workshop, 2022.
N. Firouzian, S. H. Mozafari, J. J. Clark, W. J. Gross, and B. H. Meyer,
“Latency and accuracy predictors for efficient BERT hardware-aware NAS,” in 2022 edge intelligence workshop, 2022.
M. L. Kornelsen, S. H. Mozafari, J. J. Clark, B. H. Meyer, and W. J. Gross,
“ARMCL BERT: Novel quantizable BERT implementation for ARM SoCs,” in 2022 edge intelligence workshop, 2022.
C. Li, S. H. Mozafari, J. J. Clark, W. J. Gross, and B. H. Meyer,
“ARMCL BERT: Novel quantizable BERT implementation for ARM SoCs,” in 2022 edge intelligence workshop, 2022.
C. Le, A. Ardakani, J. J. Clark, B. H. Meyer, and W. J. Gross,
“Dyadic integer only BERT,” in 2022 edge intelligence workshop, 2022.
L. Shen, B. H. Meyer, W. J. Gross, and J. J. Clark,
“Retention of domain adaptability in compressed neural networks,” in 2022 edge intelligence workshop, 2022.
H. Zhang, S. H. Mozafari, J. J. Clark, B. H. Meyer, and W. J. Gross,
“Towards finding efficient students via blockwise neural architecture search and knowledge distillation,” in 2022 edge intelligence workshop, 2022.
S. C. Smithson, O. S. Ahmed, G. Yang, W. J. Gross, and B. H. Meyer,
“Neural networks designing neural networks: Multi-objective hyper-parameter optimization,” in Workshop on hardware and algorithms for learning on-a-chip (HALO), 2016.
S. Arrabi, L. Wang, D. Moore, B. Calhoun, K. Skadron, J. Lach, and B. H. Meyer,
“Flexibility and circuit overheads in reconfigurable SIMD/MIMD systems,” in Proceedings of the 22nd IEEE international symposium on field-programmable custom computing machines (FCCM), 2014.
M. Liu, J. Caplan, G. Z. Kostadinov, and B. H. Meyer,
“Workload effects on execution fingerprinting for low-cost safety-critical systems,” in Semiconductor research corporation TECHCON 2013, 2013.
L. G. Szafaryn, B. H. Meyer, and K. Skadron,
“Evaluating soft error protection mechanisms in the context of multi-bit errors at the scope of a processor,” in Semiconductor research corporation TECHCON 2012, 2012.
D. A. Epstein, K. Skadron, and B. H. Meyer,
“Multi-granularity redundancy in multi-core SIMT,” in Proceedings of the 6th IEEE workshop on design for manufacturability and yield, 2012.
R. Zhang, B. H. Meyer, W. Huang, K. Skadron, and M. R. Stan,
“Some limits of power delivery in multicore era,” in Proceedings of the 4th workshop on energy-efficient design (WEED), 2012.
D. A. Epstein, K. Skadron, and B. H. Meyer,
“SIMD performance and yield optimization with multi-granularity redundancy,” in Work-in-progress poster session at the 49th IEEE/ACM design automation conference, 2012.
M. Guevar, P. Wu, M. D. Marino, J. Meng, L. G. Szafaryn, P. Satyamoorthy, B. H. Meyer, K. Skadron, J. Lach, and B. Calhoun,
“Exploiting dynamically changing parallelism with a reconfigurable array of homogeneous sub-cores,” in Semiconductor research corporation TECHCON 2010, 2010.
B. H. Meyer,
“Cost-effective lifetime and yield optimization for NoC-based MPSoCs,” in 13th ACM/SIGDA ph.d. Forum at DAC, 2010.
A. S. Hartman, B. H. Meyer, and D. E. Thomas,
“Lifetime-aware task mapping using ant colony optimization,” in Semiconductor research corporation TECHCON 2009, 2009.
B. H. Meyer, A. S. Hartman, and D. E. Thomas,
“Architecture and automation insights for system-level lifetime and yield optimization in NoC-based MPSoCs,” in Proceedings of the 3rd IEEE workshop on design for manufacturability and yield, 2009.
B. H. Meyer and D. E. Thomas,
“Reliability and cost in NoC-based MPSoCs,” in Semiconductor Research Corporation TECHCON 2008, 2008.
B. H. Meyer and D. E. Thomas,
“Simultaneous synthesis of buses, data mapping and memory allocation for MPSoC,” in Semiconductor Research Corporation TECHCON 2007, 2007.
J. M. Paul and B. H. Meyer,
“Systems, speedup and heterogeneity,” in Proceedings of the 3rd workshop on application specific processors, 2004.

Book Chapters

J. M. Paul and B. H. Meyer,
“Power-performance modeling and design for heterogeneous multiprocessors,” in Designing embedded processors, Springer, 2007, pp. 423–448.