Seyyed Hasan Mozafari

Publications

 

Journal Papers

S. H. Mozafari, B. H. Meyer, "Hot Sparing for Lifetime-Chip-Performance and Cost Improvement in Application Specific SIMT Processors," submitted to Sustainable Computing: Informatics and Systems, 2019.

S. H. Mozafari, B. H. Meyer, "Characterizing the Effectiveness of Hot Sparing on Cost and Performance-per-Watt in Application Specific SIMT," to appear in Integration the VLSI journal, 2019.

S. H. Mozafari, B. H. Meyer, "Efficient Performance Evaluation of Multi-core SIMT Processors with Hot Redundancy," in IEEE Transactions on Emerging Topics in Computing, vol. 6, no. 4, pp. 498-510, 1 Oct.-Dec. 2018.

MARIA ISABEL MERA, JONAH CAPLAN, SEYYED HASAN MOZAFARI, BRETT H. MEYER, and PETER MILDER, "Area, Throughput and Power Trade-offs for FPGA- and ASIC-based Execution Stream Compression," ACM Trans. Embed. Comput. Syst. 16, 4, Article 96 (May 2017).

Tooraj Nikoubin, Mahdieh Grailoo, and Seyyed Hasan Mozafari, "Cell Design Methodology Based on Transmission Gate for Low-Power High-Speed Balanced XOR-XNOR Circuits in Hybrid-CMOS Logic Style," Journal of Low Power Electronics, 6, 513-520 (2010). doi

N. Mirashe, A. R. Moghaddamfar, S. H. Mozafari, "The determinants of matrices constructed by subdiagonal, main diagonal and superdiagonal," Lobachevskii Journal of Mathematics, 31(3), 295-306, 2010. doi pdf

N. Mirashe, A. R. Moghaddamfar, S. H. Mozafari, S. M. H. Pooya, S. Navid Salehy and S. Nima Salehy, "Constructing new matrices and investigating their determinants," Asian-European Journal of Mathematics, 1(4), 575-588, 2008. doi

Conference Papers

S. H. Mozafari, B. H. Meyer, "Hot spare components for performance-cost improvement in multi-core SIMT," in Defect and Fault Tolerance in VLSI , 2015. doi pdf

S. H. Mozafari, B. H. Meyer, K. Skadron, "Yield-aware performance-cost characterization for multicore SIMT," in Great Lakes Symposium on VLSI, 2015. doi pdf

S. H. Mozafari, M. Fazeli, S. Hessabi, S. G. Miremadi, "A Low Cost Circuit level Fault Detection Technique to Full Adder Design," 18th edition of the IEEE International Conference on Electronics, Circuits, and Systems, 2011. doi pdf

Patents

"Design and Implementation of Viterbi Soft Decoder with the Highest Possible Correcting Capability Among Other Viterbi Decoders", filed Oct. 25, 2011, file No. 73009. S. H. Mozafari, M. J. Emadi, S. A. Nezamalhossieni, 2011.